Acceptor - An element, such as boron, indium, and gallium used to create a free hole in a semiconductor. The acceptor atoms are required to have one less valence electron than the semiconductor.
　　受主 - 一種用來(lái)在半導(dǎo)體中形成空穴的元素，比如硼、銦和鎵。受主原子必須比半導(dǎo)體元素少一價(jià)電子
　　
　　Alignment Precision - Displacement of patterns that occurs during the photolithography process.
　　套準(zhǔn)精度 - 在光刻工藝中轉(zhuǎn)移圖形的精度。
　　
　　Anisotropic - A process of etching that has very little or no undercutting
　　各向異性 - 在蝕刻過(guò)程中，只做少量或不做側(cè)向凹刻。
　　
　　Area Contamination - Any foreign particles or material that are found on the surface of a wafer. This is viewed as discolored or smudged, and it is the result of stains, fingerprints, water spots, etc.
　　沾污區(qū)域 - 任何在晶圓片表面的外來(lái)粒子或物質(zhì)。由沾污、手印和水滴產(chǎn)生的污染。
　　
　　Azimuth, in Ellipsometry - The angle measured between the plane of incidence and the major axis of the ellipse.
　　橢圓方位角 - 測(cè)量入射面和主晶軸之間的角度。
　　
　　Backside - The bottom surface of a silicon wafer. (Note: This term is not preferred; instead, use ‘back surface’.)
　　背面 - 晶圓片的底部表面。（注：不推薦該術(shù)語(yǔ)，建議使用“背部表面”）
　　
　　Base Silicon Layer - The silicon wafer that is located underneath the insulator layer, which supports the silicon film on top of the wafer.
　　底部硅層 - 在絕緣層下部的晶圓片，是頂部硅層的基礎(chǔ)。
　　
　　Bipolar - Transistors that are able to use both holes and electrons as charge carriers.
　　雙極晶體管 - 能夠采用空穴和電子傳導(dǎo)電荷的晶體管。
　　
　　Bonded Wafers - Two silicon wafers that have been bonded together by silicon dioxide, which acts as an insulating layer.
　　綁定晶圓片 - 兩個(gè)晶圓片通過(guò)二氧化硅層結(jié)合到一起，作為絕緣層。
　　
　　Bonding Interface - The area where the bonding of two wafers occurs.
　　綁定面 - 兩個(gè)晶圓片結(jié)合的接觸區(qū)。
　　
　　Buried Layer - A path of low resistance for a current moving in a device. Many of these dopants are antimony and arsenic.
　　埋層 - 為了電路電流流動(dòng)而形成的低電阻路徑，攙雜劑是銻和砷。
　　
　　Buried Oxide Layer (BOX) - The layer that insulates between the two wafers.
　　氧化埋層(BOX) - 在兩個(gè)晶圓片間的絕緣層。
　　
　　Carrier - Valence holes and conduction electrons that are capable of carrying a charge through a solid surface in a silicon wafer.
　　載流子 - 晶圓片中用來(lái)傳導(dǎo)電流的空穴或電子。
　　
　　Chemical-Mechanical Polish (CMP) - A process of flattening and polishing wafers that utilizes both chemical removal and mechanical buffing. It is used during the fabrication process.
　　化學(xué)-機(jī)械拋光(CMP) - 平整和拋光晶圓片的工藝，采用化學(xué)移除和機(jī)械拋光兩種方式。此工藝在前道工藝中使用。
　　
　　Chuck Mark - A mark found on either surface of a wafer, caused by either a robotic end effector, a chuck, or a wand.
　　卡盤痕跡 - 在晶圓片任意表面發(fā)現(xiàn)的由機(jī)械手、卡盤或托盤造成的痕跡。
　　
　　Cleavage Plane - A fracture plane that is preferred.
　　解理面 - 破裂面
　　
　　Crack - A mark found on a wafer that is greater than 0.25 mm in length.
　　裂紋 - 長(zhǎng)度大于0.25毫米的晶圓片表面微痕。
　　
　　Crater - Visible under diffused illumination, a surface imperfection on a wafer that can be distinguished individually.
　　微坑 - 在擴(kuò)散照明下可見(jiàn)的，晶圓片表面可區(qū)分的缺陷。
　　
　　Conductivity (electrical) - A measurement of how easily charge carriers can flow throughout a material.
　　傳導(dǎo)性（電學(xué)方面） - 一種關(guān)于載流子通過(guò)物質(zhì)難易度的測(cè)量指標(biāo) 。